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SECURE-IC

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In accordance with Swiss entry regulation, everyone entering Switzerland must present an entry form. If you are not vaccinated or recovered, you must also show proof of a negative test. Please check the requirements to enter Switzerland and ensure the compliance to them.

In accordance with Swiss regulations and USI COVID-19 campus protection provisions, a COVID certificate will be required for accessing COSADE 2021 and checks will be enforced every day at the entrance; a valid COVID certificate is also required to access restaurants, in particular the one of the social event. Face masks are also mandatory in all indoor areas of the university campus.

Workshop Program

Monday, October 25

Conference at USI, Lugano

13:00

Registration Opens

14:00

Opening and Welcome Address

Francesco Regazzoni, Alberto Ferrante, Subhadeep Banik (General Chairs)

Shivam Bhasin, Fabrizio De Santis (Program Chairs)

14:15

Keynote 1: Massimo Alioto (National University of Singapore)

Securing the Next Trillion of Chips via In-Memory and Immersed-in-Logic Design - Beyond Traditional Design Boundaries

15:30

Coffee break

15:55

Session 1: Side-Channel Attacks

Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia and Philippe Loubet Moundi: SideLine: How Delay-Lines (May) Leak Secrets from your SoC

Yaacov Belenky, Yury Kremer, Leonid Azriel, Ira Dushar, Valery Teper and Hennadii Chernyshchyk: First Full-fledged Side Channel Attack on HMAC-SHA-2

Guilherme Perin, Ileana Buhan and Stjepan Picek: Learning when to stop: a mutual information approach to prevent overfitting in profiled side-channel analysis

17:10

Coffee break

17:35

Session 2: Fault Attacks

Sayandeep Saha and Debdeep Mukhopadhyay: Transform without Encode is not sufficient for SIFA and FTA security: A Case Study

Guillaume Barbu, Laurent Castelnovi and Thomas Chabrier: Generalizing Statistical Ineffective Fault Attacks in the Spirit of Side-Channel Attacks

18:30

Welcome cocktail

Tuesday, October 26

Conference at USI, Lugano

09:00

Registration Opens

10:00

Keynote 2: Alberto Sangiovanni-Vincentelli (University of California at Berkeley)

Defending CyberPhysical Systems and Infrastructures from Cyber Attacks

11:15

Coffee break

11:40

Session 3: Post-Quantum Cryptography

Aurelien Greuet, Simon Montoya and Guénael Renault: On Using RSA/ECC Coprocessor for Ideal Lattice-Based Key Exchange

Novak Kaluderovic, Aymeric Genet and Natacha Linard de Guertechin: Full key recovery side-channel attack against ephemeral SIKE on the Cortex-M4

Elise Tasso, Luca De Feo, Nadia El Mrabet and Simon Pontie: Resistance of Isogeny-Based Cryptographic Implementations to a Fault Attack

12:55

Lunch break

14:10

Industrial Session 1:

Michael Tempelmeier: Introduction to OpenTitan -- An Open-Source Silicon Root of Trust Project

Charlotte Bonte, Rosario Cammarota, Wei Dai, Joshua Fryman, Huijing Gong, Duhyeong Kim, Raghavan Kumar, Kim Laine, Poornima Lalwaney, Sanu Mathew, Nojan Sheybani, Anand Rajan, Andrew Reinders, Michael Steiner, Vikram Suresh, Sachin Taneja, Marc Trifan, Alexander Viand, Wei Wang, Wen Wang, Chris Wilkerson, and Jin Yang: Is Revolutionary Hardware for Fully Homomorphic Encryption important? What else is needed?

15:00

Coffee break

15:25

Industrial Session 2:

Joppe W. Bos, Joost Renes, and Christine van Vredendaal: Post-Quantum Cryptography with Contemporary Co-Processors

Sylvain Guilley and Sofiane Takarabt: Analyzing the Harmfulness of Glitches in the Context of Side-Channel Analysis

16:20

Social Event

Visit at Swissminiatur followed by Dinner at Ristorante della Torre

Wednesday, October 27

Conference at USI, Lugano

09:00

Registration Opens

10:00

Session 4: Physical Unclonable Functions

Lars Tebelmann, Ulrich Kuhne, Jean-Luc Danger and Michael Pehl: Analysis and Protection of the Two-metric Helper Data Scheme

Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger and Naghmeh Karimi: Enhancing the Resiliency of Multi-Bit Parallel Arbiter-PUF and its Derivatives against Power Attacks

10:50

Coffee break

11:15

Session 5: Countermeasures

Davide Poggi, Philippe Maurine, Thomas Ordas and Alexandre Sarafianos: Protecting secure ICs against side-channel attacks by identifying and quantifying potential EM and leakage hotspots at simulation stage

Nicolai Muller, Thorben Moos and Amir Moradi: Low-Latency Hardware Masking of PRINCE

Balazs Udvarhelyi, Olivier Bronchain and Francois-Xavier Standaert: Security Analysis of Deterministic Re-Keying with Masking & Shuffling: Application to ISAP

Agathe Houzelot, Christophe Giraud and Emmanuelle Dottax: White-Box ECDSA: Challenges and Existing Solutions

12:55

Closing remarks

Francesco Regazzoni, Alberto Ferrante, Subhadeep Banik (General Chairs)

13:00

Lunch


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Università della Svizzera italiana