EMERTECH will take place on April 25, 2018 (after COSADE).
Venue: CREATE Auditorium
General Chair: Anupam Chattopadhyay, Kwok Yan Lam
Multiple emerging technologies, e.g., graphene, Spintronics and resistive RAM are being developed to enhance the capabilities of logic devices, circuits and architectures resulting in an increasing energy-efficiency and better reliability. These devices enable very different computing paradigm, e.g., in-memory computing and at the same time, open up new side channels that requires careful analysis before using those as implementation platforms for cryptographic primitives. In this workshop, we will cover both design and attack aspects for different emerging technologies; and also get a sneak preview of the frontiers of nanotechnology. The topics of interest include, but not limited to, the following.
Designing efficient cryptographic primitives with emerging technologies
Side channel attacks for emerging technologies
Device/Circuit perspectives for emerging technologies
Beyond Von Neumann architectures: (neuromorphic, in-memory computing)
[8:45-9:00] Opening Remarks
[9:00-9:45] Subhasish Mitra (Stanford, USA):
Transforming Nanodevices into Nanosystems: The N3XT 1,000X
[10:30-11:15] Shahar Kvatinsky (Technion, Israel):
Real Processing-in-Memory with Memristive Memory Processing Unit
[9:45-10:30] Andrea Calimera (Torino, Italy):
Beyond CMOS-like circuits with emerging devices: logic synthesis and optimization for ultra-low power applications
11:15-12:00 Lunch Break
[12:00-12:45] Avi Mendelson (Technion, Israel):
Impact of new process technologies on the achievable security of future chips
[13:30-14:15] Shivam Bhasin (Temasek Labs @ NTU, Singapore):
Side-Channel Attack on STTRAM based Cache for Cryptographic Application
[12:45-13:30] Arindam Basu (NTU, Singapore):
When Physical Unclonable Function (PUF) meets Machine Learning
14:15-14:45 Tea Break
[14:45-15:30] Manas Mukherjee (NUS, Singapore):
Quantum technology – the future looks bright
[15:30-16:15] Francesco Regazzoni (USI, Switzerland):
Quantum Computer and Cryptography: Threats, Challenges, and Opportunities
[16:15-17:30] Debdeep Mukhopadhyay (IIT Kharagpur, India):
Every Malware Leaves a Trace: Hardware Monitoring for Malwares in Computer Systems
[17:30-17:45] Closing Remarks
Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computation demands of these abundant-data applications far exceed the capabilities of today’s electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency. However, emerging nanomaterials and nanodevices face major obstacles such as inherent imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible.
The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive and magnetic memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal.
N3XT hardware prototypes represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual nanosystems. Compared to conventional approaches, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems to the cloud.
Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Prof. Mitra holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI in Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation.
Prof. Mitra’s research interests range broadly across robust computing, nanosystems, VLSI design, validation, test and electronic design automation, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first three-dimensional nanosystem with computation immersed in data storage. These demonstrations received wide-spread recognitions (cover of NATURE, Research Highlight to the United States Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.
Prof. Mitra’s honors include the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors “for being important to them during their time at Stanford.”
Prof. Mitra served on the Defense Advanced Research Projects Agency’s (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE).
Memristive technologies are attractive candidates to replace conventional memory technologies, and can also be used to perform logic and arithmetic operations using a technique called ‘stateful logic.’ Combining data storage and computation in the memory array enables a novel non-von Neumann architecture, where both the operations are performed within a memristive Memory Processing Unit (mMPU). mMPU relies on adding computing capabilities to the memristive memory cells without changing the basic memory array structure. The use of an mMPU alleviates the primary restriction on performance and energy in von Neumann machine, which is the data transfer between CPU and memory.
This talk focuses on the various aspects of mMPU. I will discuss its architecture and implications on the computing system and software, as well as examining the microarchitectural aspects. I will show how to design the mMPU controller and how different sequence of computing operations in an mMPU can be automatically optimized as sequences of basic Memristor Aided Logic (MAGIC) NOR and NOT operations. Then, I will present examples of applications that can benefit from processing within memristive memory and show how adding mMPU to conventional computing systems substantially improves the system performance and energy efficiency.
Shahar Kvatinsky is an assistant professor at the Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion – Israel Institute of Technology. He received the B.Sc. degree in computer engineering and applied physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in electrical engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009 he was with Intel as a circuit designer and was a post-doctoral research fellow at Stanford University from 2014 to 2015. Kvatinsky is an editor in Microelectronics Journal and has been the recipient of the 2015 IEEE Guillemin-Cauer Best Paper Award, 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, ERC starting grant, the 2017 Pazy Memorial Award, the 2014 and 2017 Hershel Rich Technion Innovation Awards, 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and six Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and design of energy efficient architectures.
With the rise of new applications and new computing paradigms, the ICT industry is called to face a paramount challenge: rethink hardware design including all the aspects, from devices to systems. At the device-level, several emerging technologies have already shown disruptive electrical and functional properties that will bring computation to the next level. Nevertheless, their integration at a large-scale still is an open issue.
Aim of this talk is to introduce design alternatives for emerging devices, Graphene-based devices in particular. The presentation shows how integration strategies other than those adopted in today’s VLSI circuits may represent a viable path towards ultra-low power computational logic. New abstract models, their optimization, and the resulting synthesis flow are discussed and compared against state-of-art design strategies for some emerging applications.
Andrea Calimera is an Associate Professor at the Department of Control and Computer Engineering, Politecnico di Torino, Italy. He received the M.S. degree (summa cum laude) in Electronic Engineering and the Ph.D. degree in Computer Engineering from Politecnico di Torino. His main research interests focus on the design automation of digital ICs, with particular emphasis on methods and CAD tools for low-power, energy-efficient, and reliable circuits for embedded architectures implemented with standard CMOS technologies and emerging devices.
The anticipation of the “end of moor’s law area” drives the market to looking at new process technologies; e.g., Memristors, Graphite and new architecture solutions; e.g., many-cores, multi-cores, PIM.
This talk will mainly focus at the impact of these technologies on the achievable security of future systems. The talk will start with a short description of some of the future technologies and continue with a discussion on the pros and cons of each technology on future trends in security.
At the end of the talk will be devoted for research opportunities in these areas for both the industry as well as for graduate students
Prof. Avi Mendelson has a blend of industrial and academic experience in several different areas such as computer architecture, real-time systems, power management, reliability and Hardware security. He received a PhD from the ECE Department University of Massachusetts at Amherst (UMASS) in 1990 and his BSC and MSC degrees from the Computer Science department, Technion
Among his industrial jobs, he worked for 11 years as a senior researcher and principle engineer at Intel, among his achievements there; he was the chief architect of the CMP (multicore-on-chip) feature of the first dual core processors Intel developed. For this work, he received the Intel Achievement Award (the highest award at Intel).
Currently he is serving as a visiting professor at the CS and EE departments at the Technion and as a visiting professor at NTU, Singapore. Among his academic activities he teach and supervise students in various areas related to hardware security, computer Architecture, accelerators for deep learning, and more. Recently, the Technion opened a new center for cyber security, where he is leading much of the activities around hardware security.
Prof. Avi Mendelson is a IEEE fellow, he has published more than 130 papers in refereed journals, conferences, and workshops. He serves as an associate editor of IEEE Transactions on Computers, as a general chair of ISCA’2013(International Symposium on Computer Architecture) in 2013, and a program chair of different conferences, including ICS-2018 that will take place next year in.
In this paper, we propose a Side Channel Attack (SCA) model on Spin-Torque Transfer RAM (STTRAM) where an adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. Simulation results indicate that by monitoring write current, 50% of keys could be extracted using 2000 traces. Further improvement of attacks on write operation is also proposed. The read current is found to be more susceptible to leak the key. It reveals first byte in only 40 traces and leaks the entire key in as low as 400 traces. The results are then compared with SRAM based cache. The attack model has been experimentally validated on read operation of commercial MRAM chip (a variant of STTRAM). Experimental results indicate that the attack can reveal correct key in 15 traces compared to 40 in simulation due to less algorithmic noise. To the best of our knowledge, this is the first comprehensive SCA study for STTRAM based cache for cryptographic application.
Shivam Bhasin is a Senior Research Scientist at Temasek Lab, Nanyang Technological University Singapore since 2015. His research interests include embedded security, trusted computing and secure designs. He received his PhD from Telecom Paristech in 2011, Master’s from Mines Saint-Etienne, France in 2008 and Bachelor’s from UP Tech, India in 2007. Before NTU, Shivam held position of Research Engineer in Institut Mines-Telecom, France. He was also a visiting researcher at UCL, Belgium (2011) and Kobe University (2013). He has co- authored several publications at recognized journals and conferences. Shivam served in sTPCs of several conferences, regularly reviews journal/ conference articles and presented multiple invited seminars/tutorials in prestigious venues. Some of his research now also forms a part of ISO/IEC 17825 standard. He is also part of ESP Pvt Ltd, a budding start up on Hardware Security.
In this talk, we first review the concept of PUF and show some popular designs. We then describe a current mirror array (CMA) based PUF and show its connections with some machine learning algorithms based on random neural networks. Next, we show how to improve the machine learning attack resistance of the PUF using concepts from neural networks. Finally, we show how emerging devices can be used to make this PUF.
Arindam Basu received the B.Tech and M.Tech degrees in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur in 2005, the M.S. degree in Mathematics and PhD. degree in Electrical Engineering from the Georgia Institute of Technology, Atlanta in 2009 and 2010 respectively. Dr. Basu received the Prime Minister of India Gold Medal in 2005 from I.I.T Kharagpur. He joined Nanyang Technological University in June 2010 and currently holds a tenured Associate Professor position.
He is currently an Associate Editor of IEEE Sensors journal, IEEE Transactions on Biomedical Circuits and Systems and Frontiers in Neuroscience. He was a Distinguished Lecturer for IEEE Circuits and Systems Society for the 2016-17 term. He was also a guest editor for two Special Issues in IEEE Transactions on Biomedical Circuits and Systems for selected papers from ISCAS 2015 and BioCAS 2015. Dr. Basu received the best student paper award at Ultrasonics symposium, 2006, best live demonstration at ISCAS 2010 and a finalist position in the best student paper contest at ISCAS 2008. He was awarded MIT Technology Review’s inaugural TR35@Singapore award in 2012 for being among the top 12 innovators under the age of 35 in SE Asia, Australia and New Zealand. His research interests include bio-inspired neuromorphic circuits, non-linear dynamics in neural systems, low power analog IC design and programmable circuits and devices. He is serving as Corresponding Guest Editor for the Special Issue on “Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms” in the IEEE Journal on Emerging Topics in Circuits and Systems.
Centre for Quantum Technologies NUS, Singapore, Department of Physics, NUS, Singapore, Majulab CNRS, Singapore
Quantum mechanics is fundamentally different from the more conventional classical mechanics that we know of, and we have used in developing technology so far. The technology that involves quantum laws is operationally closer to the functioning of the basic building blocks of nature. Therefore, the operational limits of quantum technology are given by the fundamental laws of nature. Certain technologies based on quantum mechanics are already very mature such as lasers, scanning tunnelling microscope etc. However, technological development using more subtle quantum resources like entanglement is poised to make a second quantum revolution. The devices based on quantum laws encompass different fields including sensing, computing and communication. These three technologies are in different states of development and all are considered to be emerging technologies which will re-shape the technology landscape. I’ll be reviewing the developments in quantum computing and sensing while touch upon communication in a broader perspective. In addition, I intend to provide the emerging landscape of quantum technologies in Singapore in the context of the rest of the world.
Dr. Manas Mukkherjee got his PhD in Natural Sciences from the University of Heidelberg Germany. He was awarded the Lise-Meitner research fellowship from the National Research Foundation, Austria. There he worked with Prof. Rainer Blatt on the problem of generating and using entanglement between an atom and a Photon. He was also a Max Planck international research fellow between 2009 and 2012. Since 2012 he is leading an experimental research group in developing quantum technologies using trapped ions at the Centre for Quantum Technologies, NUS Singapore.
Speaker: Francesco Regazzoni, USI
The security of cryptographic algorithms is based on hardness assumptions. They aim to ensure that an adversary cannot solve the underlying hard problem even with a vast amount of resources. Until recently, these assumptions mainly concentrated on the intractability of solution with respect to a classical computing paradigm. However, the aggressive pursuit of quantum technology has forced a fundamental rethink in the underlying problems upon which cryptosystems are built.
As a result, the cryptographic community is preparing for a major transition in public key cryptosystems to quantum safe alternatives. Several standardization bodies are in the process of evaluating and standardizing quantum safe (or post quantum) algorithms to replace traditional ones. Still, quantum safe constructions have to be studied in depth and their performance and side channel resistance have to be asserted.
This talk will discuss the problem of security in the quantum era, discussing the effects that quantum computation power will have on existing cryptographic primitives, and will highlight, form a designer point of view, challenges and opportunities related with the transition towards quantum safe cryptography.
Dr. Francesco Regazzoni is a senior researcher at the AlaRI Institute of University of Lugano. He received his Master of Science degree from Politecnico di Milano and his PhD degree from University of Lugano. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft, and visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, and EPFL Lausanne. His research interests are mainly focused on secure IoT devices and embedded systems, covering in particular design automation for security, physical attacks and countermeasures, post-quantum cryptography, and efficient implementation of cryptographic primitives.
In computer science there is often a disconnect between software and hardware, while software development is in reality programming a specific hardware platform. Understanding this aspect, can have profound impact on security, more specifically in detecting malwares. Although there has been an array of malware detection tools, they have unfortunately largely been restricted to observing high-level events and software API calls. In this talk, we highlight the role of low-level hardware events derived from so-called Hardware Performance Counters (HPCs) present in modern day computer architectures for detection of the execution of malwares. We discuss two case studies. One in context to embedded platforms, where we discuss on the usage of statistical hypothesis testing for developing a lightweight test using HPC values to evaluate a program under test as a potential malware. While in the other case, we discuss an extremely fast detection methodology for popular ransomwares (a malware which encrypts _les and asks for ransom) on standard desktops. The detection methodology performs a combined analysis using Artificial Neural Network (ANN) and Fast Fourier Transform (FFT) to develop a very fast detection tool which can potentially detect well known ransomwares even before one file gets encrypted. Our detection methodology templates the benign environment and is not dependent on specific signatures generated from known malwares, and is thus expected to be capable of performing well against unreported malwares. We present extensive experimental data throughout the presentation to corroborate the claims made.
Debdeep Mukhopadhyay is currently a full Professor at the Department of Computer Science and Engineering, IIT-Kharagpur, India. At IIT Kharagpur he initiated the Secured Embedded Architecture Laboratory (SEAL), with a focus on Embedded Security and Side Channel Attacks. Prior to this he worked as Associate Professor at IIT Kharagpur, visiting scientist at NTU Singapore, a visiting Associate Professor of NYU-Shanghai, Assistant Professor at IIT-Madras, and as Visiting Researcher at NYU Tandon-School-of-Engineering, USA. He holds a PhD, an MS, and a B. Tech from IIT Kharagpur, India. Dr. Mukhopadhyay’s research interests are Cryptography, Hardware Security, and VLSI. His books include Fault Tolerant Architectures for Cryptography and Hardware Security (Springer), Cryptography and Network Security (McGraw Hills), Hardware Security: Design, Threats, and Safeguards (CRC Press), and Timing Channels in Cryptography (Springer). He has written more than 150 papers in peer-reviewed conferences and journals and has collaborated with several Indian and Foreign Organizations. He is in the program committee of several top International conferences and is an Associate Editor of the International Association of Cryptologic Research (IACR) Transactions of CHES, Journal of Hardware and Systems Security, Springer. Dr. Mukhopadhyay is the recipient of the prestigious Swarnajayanti DST Fellowship 2015-16, Young Scientist award from the Indian National Science Academy, the Young Engineer award from the Indian National Academy of Engineers, and is a Young Associate of the Indian Academy of Science. He was also awarded the Outstanding Young Faculty fellowship in 2011 from IIT Kharagpur, and the Techno-Inventor Best PhD award by the Indian Semiconductor Association. He has recently incubated a start-up on Hardware Security, ESP Pvt Ltd at IIT Kharagpur.